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first edition issue date : jan. 1999 data sheet ? msm60804 pcmcia host adapter
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1999 oki electric industry co., ltd. printed in japan e2y0002-29-11
table of contents general description ........................................................................................ 1 features ................................................................................................................ 1 block diagram .................................................................................................... 2 pin configuration (top view) ......................................................................... 3 pin description ................................................................................................... 6 absolute maximum ratings ......................................................................... 11 recommended operating conditions ..................................................... 11 electrical characteristics ....................................................................... 12 timing diagram .................................................................................................. 14 functional description ................................................................................ 18 registers ............................................................................................................. 23
1/50 msm60804 ? semiconductor general description the msm60804 pcmcia host adapter is a pcmcia host interface chip capable of controlling two pcmcia sockets. the msm60804 is compatible with indutry standard 82365sl functions. features ? functionally compatible with 82365sl ? isa bus interface ? compliance with pcmcia 2.1/jeida 4.2 ? mixed-voltage (3.3 v or 5.5 v) operation ? dual pcmcia socket interface:208-pin qfp ? 8-bit or 16-bit access supported ? complies with both memory card and i/o card ? range of window setting: 64kb i/o access space (0-ffffh) 64mb memory access space (0-3ffffffh) (common, attribute) ? one of irq3, irq4, irq5, irq7, irq9, irq10, irq11, irq12, irq14, irq15, and iochck can be allocated to each slot ? power supply control to each slot is available (5 v card and 3 v card are supported) ? card power down control ? 4 slots are available by cascade connection ? package: 208-pin plastic qfp (qfp208-p-2828-0.50-k4) (product name:MSM60804GS-K4) ? semiconductor msm60804 pcmcia host adapter this version: jan. 1999 e2n0030-19-11
2/50 msm60804 ? semiconductor control signals address bus data bus memory/ i/o mmu system interface control register wait control interrupt control memory map register card control & buffer socket power control card status detection card status detection card control & buffer memory map register memory/ i/o mmu address bus data bus control signal status signal status signal control signal data bus address bus 24 16 26 16 16 26 pcmcia slot pcmcia slot socket power control block diagram figure 1 msm60804 block diagram
3/50 msm60804 ? semiconductor pin configuration (top view) ardy awp awat acd1 acd2 abv1 abv2 ace1 ace2 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 av10 gnd av11 vcca ad6 ad5 ad4 ad3 avss0 avss1 ad2 ad1 ad0 aa25 aa24 aa23 aa22 aa21 aa20 aa19 avccen0 avccen1 vcca aa18 aa17 aa16 aa15 gnd aa14 aa13 aa12 aa11 aa10 aa9 vcccore sa11 sa12 sa13 isapwr ichk memr sa1 sa2 sa3 irq5 irq4 irq3 bale d0 iord d1 d2 gnd spkr/sel0 irdy gnd memw ic16 mc16 iowr sa0 irq10 irq9 irq7 sa4 sa5 sa6 sa7 vccisa d3 gnd d4 d5 d6 sa8 sa9 sa10 sclk irq15 irq14 irq12 irq11 sa14 sa15 sa16 d7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 aa8 aa7 aa6 aa5 aa4 aa3 aa2 aa1 aa0 areg aiow arst aior awe aoe brdy bwp bwat bcd1 bcd2 bbv1 bbv2 bce1 bce2 bd15 bd14 bd13 bd12 bd11 bd10 bd9 bd8 bd7 bv10 gnd bv11 vccb bd6 bd5 bd4 bd3 bvss0 bvss1 bd2 bd1 bd0 ba25 ba24 ba23 ba22 ba21 ba20 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 gnd d8 d9 vccisa d10 la17 la18 la19 la20 la21 la22 la23 d11 d12 d13 gnd d14 d15 rstd nws sbhe aen boe bwe bior brst biow breg ba0 ba1 ba2 ba3 ba4 ba5 ba6 ba7 ba8 ba9 ba10 ba11 ba12 ba13 ba14 gnd ba15 ba16 ba17 ba18 vccb bvccen1 bvccen0 ba19 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 208-pin plastic qfp
4/50 msm60804 ? semiconductor pin list pin number signal name pin number signal name pin number signal name pin number signal name ardy ad0 aa0 bd5 131 awp aa25 areg bd4 232 awat aa24 aiow bd3 333 acd1 aa23 arst bvss0 434 acd2 aa22 aior bvss1 535 abv1 aa21 awe bd2 636 abv2 aa20 aoe bd1 737 ace1 aa19 brdy bd0 838 ace2 avccen0 bwp ba25 9 ad15 avccen1 bwat ba24 10 ad14 vcca bcd1 ba23 11 ad13 aa18 bcd2 ba22 12 ad12 aa17 bbv1 ba21 13 ad11 aa16 bbv2 ba20 14 ad10 aa15 bce1 ba19 15 ad9 gnd bce2 bvccen0 16 ad8 aa14 bd15 bvccen1 17 ad7 aa13 bd14 vccb 18 av10 aa12 bd13 ba18 19 gnd aa11 bd12 va17 20 av11 aa10 bd11 ba16 21 vcca aa9 bd10 ba15 22 ad6 aa8 bd9 gnd 23 ad5 aa7 bd8 ba14 24 ad4 aa6 bd7 ba13 25 ad3 aa5 bv10 ba12 26 avss0 aa4 gnd ba11 27 avss1 aa3 bv11 ba10 28 ad2 aa2 vccb ba9 29 ad1 aa1 bd6 ba8 30 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 91 62 92 63 93 64 94 65 95 66 96 67 97 68 98 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
5/50 msm60804 ? semiconductor pin number signal name pin number signal name pin number signal name pin number signal name ba7 d12 sclk gnd 121 143 ba6 d11 sa10 irdy 122 144 ba5 la23 sa9 spkr /sel0 123 145 ba4 la22 sa8 gnd 124 146 ba3 la21 d6 d2 125 147 ba2 la20 d5 d1 126 148 ba1 la19 d4 iord 127 149 ba0 la18 gnd d0 128 150 breg la17 d3 bale 129 biow d10 vccisa irq3 130 brst vccisa sa7 irq4 131 bior d9 sa6 irq5 132 bwe d8 sa5 sa3 133 boe gnd sa4 sa2 134 aen d7 irq7 sa1 135 sbhe sa16 irq9 memr 136 nws sa15 irq10 ichk 137 rstd sa14 sa0 isapwr 138 d15 irq11 iowr sa13 139 d14 irq12 mc16 sa12 140 gnd irq14 ic16 sa11 141 d13 irq15 memw vcccore 142 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 187 166 188 167 189 168 190 169 191 170 192 171 193 172 194 173 174 175 176 177 178 179 180 181 182 183 184 185 186 195 196 197 198 199 200 201 202 203 204 205 206 207 208 pin list (continued)
6/50 msm60804 ? semiconductor pin description symbol i description 24 drive current (ma) system interface pins la [23 : 17] sa [16 : 0] i/o pin count system address bus the address bus lines of host system interface. these lines enable direct addressing of the 16mb memory space on the card. in the word access mode, sa0 is not used. these lines are connected to la[23:17] and sa[16:0] of the 16-bit isa system. i/o 16 d [15 : 0] 16 i 1 rstd i 1 isapwr i 1 bale i 1 sclk i 1 iowr i 1 iord system data bus the bidirectional 16-bit data bus lines of host system interface. the lower byte d[7:0] is also used to access a register in the pcic. when the msm60804 is connected to an 8-bit system, pins of the higher byte are pulled up. system reset drive an active-high system reset signal this signal is used to reset the pcic and also drive the base address select signal of a register in the pcic. isa power supply this pin selects an interface type of pins connected to the system: high for 5 v ttl interface or low for the other interface type (3 v ttl interface or 5 v/3 v cmos interface). this pin is internally pulled up. bus address latch enable this pin is active high and used to latch la[23:17] at the start of bus cycle timing. system clock a system clock input of the isa this pin determines ichk timing and memr and memw delays in 16-bit accessing. the pulse width of ichk is three times as wide as the clock cycle. when a bus cycle wait is set by a register, the pulse width of irdy is equal to one sclk (1 wait). i/o port write an active-low i/o write signal this pin drives data output to an i/o port pointed to by a system address. i/o port read an active-low i/o read signal this pin drives data input from an i/o port pointed to by a system address.
7/50 msm60804 ? semiconductor symbol description system interface pins i/o i 1 memw i 1 memr od 1 mc16 16 i 1 aen i 1 sbhe i/o-pu 1 spkr /sel0 16 od 1 nws 16 o10 irq (3-5, 7, 9- 12, 14-15) 2 o1 ichk 2 system memory write an active-low memory write signal this pin drives data output to a pc card pointed to by a system address. system memory read an active-low memory read signal this pin drives data input from a pc card pointed to by a system address. 16-bit memory select an active high signal, indicating to the host system that the pc card is in the 16-bit memory access mode. system address enable system bus high enable an active-low signal, indicating the high byte of the 16-bit system data bus register base address select this pin selects the base address of a register. this pin is driven by a system reset signal (rstd) and determines the address decode value of a register according to this input when pcics are connected in a cascade fashion. while resetting is not executed, this pin works as a speaker-out output. (this pin is a bi-directional pin.) the digital audio signal from the card is output through this pin. no-wait state an active-low signal, indicates that the pc card executes no-wait accessing this pin is disabled during a 16-bit i/o cycle, and in the other cycle, is enabled by register setting. interrupt request an active-high signal, outputting an interrupt request to the host system. each slot assigns one of the irq pins as an interrupt signal. i/o channel interrupt an active-low signal, outputting a non-maskable interrupt request (nmi) to the cpu (maskable by system hardware configuration) drive current (ma) pin count od 1 ic16 16 od 1 irdy 16 16bit i/o select an active-low signal, indicating the host system that the pc card is in the 16-bit i/o access mode. i/o channel ready an active high signal, indicating the host system that the memory or i/o bus cycle has completed. while this signal is low, the host system is requested to wait.
8/50 msm60804 ? semiconductor symbol i/o description i-pu 4 abv1, bbv1 abv2, bbv2 i-pu 2 awat , bwat i-pu 2 ardy, brdy i-pu 2 awp, bwp pcmcia card socket interface pins battery voltage detect these signals are generated by the memory card as an indication of its battery condition. the status of these pins is reflected in the card status register. the status change of these pins is available for an interrupt request using the register. status change when i/o interface is selected, bv1 signal is replaced by an active-low card status change ( stschg ). the status of this pin is reflected in the interface status register. the status change of this pin is available as an interrupt request by the register. speaker in the i/o pc card, bv2 is replaced as an active-low audio digital wavefrom 1 ( spkr ). it is connected to the speaker out pin ( spkr or sel0) to drive a host speaker. bus cycle wait an active-low wait request signal, requesting a bus cycle wait signal from a pc card to the host system. ready/busy/interrupt request in memory card mode, this signal is set active high to tell the host system that the memory pc card is ready to accept a next bus cycle. while low, this signal indicates that the memory pc card is busy processing previous bus cycle and not available to execute a next bus cycle. the status of this pin is reflected in the register. the status change of this pin can be used as an interrupt request by reading the interface status register. write-protect/16-bit i/o-access in memory card mode, these pins detect the state of the write protect switch of a pc card. this signal, when active high, indicates the memory pc card is write-protected. to make a memory pc card without a write protect switch writable, these pins are grounded. to make a memory pc card read-only, these pins are connected to vcc. in i/o card mode, these pins are active low to indicate 16-bit i/o accessing. ( iois16 ) drive current (ma) pin count 4 acd1 , acd2 bcd1 , bcd2 card detect an active-low signal detecting proper card insertion. the status of this pin is reflected on the contents of registers. the status transition of this pin can be used as an interrupt request by register setting. i-pu
9/50 msm60804 ? semiconductor symbol i/o description to 2 aiow , biow 2 to 2 aior , bior 2 to 2 awe , bwe 2 to 2 aoe , boe 2 to 2 arst, brst 2 pcmcia card socket interface pins i-pu 4 avss1, avss0 bvss1, bvss0 i/o write an active-low signal to enable writing data to the pc card's i/o space. this signal is not available when the reg signal is inactive high. i/o read an active-low signal to enable reading data from the pc card's i/o space. this signal is not available when the reg signal is inactive high. write enable an active-low signal to enable writing data in the pc card. this signal enables writing data in common memory of the memory pc card when the reg signal is high or in attribute memory of the i/o pc card or memory pc card when the reg signal is low. output enable an active-low signal is used to gate control memory read data from the pc card. when the reg signal is high, this signal enables reading data from memory of the memory pc card and when the reg signal is low from attribute memory of the i/o pc card memory pc card. card reset active high signals reset the pc cards. these signals are set by pc ic's register. voltage sense pins these signals indicate the voltages required for the pc card. the values of these signals are reflected to the pcic register. drive current (ma) pin count to 52 aa [25 : 0] ba [25 : 0] 2 i/o 32 ad [15 : 0] bd [15 : 0] 2 to 4 ace1 , ace2 bce1 , bce2 2 to 2 areg , breg 2 card address bus this bus enables the pcic to directly access the 64m-byte memory address space on the card. card data bus a bus for transferring 16-bit data to and from the pc card. card enable these signals enable setting of 8-bit or 16-bit accessing to the pc card and enable odd-numbered or even-numbered-address bytes. these signals are combined with a0 to determine a method to access the pc card. the ce1 or ce2 output is enabled according to the register setting or iois16 setting. attribute memory select when this signal is active low, access is limited to attribute memory. when this signal is high, common memory access mode is set. in common memory access mode, accessing to the i/o pc card is disabled.
10/50 msm60804 ? semiconductor to: tristate od: open drain pu: pull up pw: power supply or grd pins. note: the above drive current values are for 5 v interface. the drive current values for 3 v interface are half of the above values. the msm60804 does not support the inpak signal of the pcmcia. symbol i/o description o8 avccen0 avccen1 bvccen0 bvccen1 av10, av11 vb10, vb11 16 pw 3 vccisa vcccore vcca, vccb gnd system interface pins: 66 card interface pins (per slot): 59 card power supply pins (per slot): 4 power supply pins: 16 total number of pins: 208 pw 4 pw 9 card power supply control and power supply pins power supply control these pins control power supplied to the pc cards and power to the buffer in the card interface of the pcic. their values are set by registers. system interface buffer / core power supply these pins supply power to the buffer and the core on the system interface side. vccisa and vcccore voltages must be equal. card interface buffer power supply these pins supply power (of the same voltage as that of power supplied to the card slot) to the buffer on the card interface side. ground drive current (ma) pin count
11/50 msm60804 ? semiconductor absolute maximum ratings parameter symbol condition rating unit supply voltage v dd C0.5 to +6.5 input voltage v i ta = 25c v ss = 0 v C0.5 to v dd + 0.5 v output voltage v o C0.5 to v dd + 0.5 input current i i C10 to +10 output current i o 2 ma buffer C25 to +25 ma C50 to +50 storage temperature t stg C65 to +150 c 16 ma buffer recommended operating conditions parameter symbol min. typ. max. unit 2.7 3.3 3.6 v 4.5 5 5.5 C40 +25 +85 c 2 20 ns supply voltage operating temperature input rise and fall times top tr, tf 3 v 5 v v dd
12/50 msm60804 ? semiconductor electrical characteristics dc characteristics 3.3 v interface note 1 : typical conditions are v dd = 3.3 v, tj = 25 c note 2 : 1 sa pwr pin should be held "low". voltage control register bit 2 should be set to "0". 5.0 v interface note 1 : typical conditions are : v dd = 3.3 v, tj = 25 c note 2 : 1 sa pwr pin should be held "high". voltage control register bit 2 should be set to "1". parameter symbol condition min. typ. max. unit "h" level input voltage v ih ttl level input (note 2) 1.8 v dd + 0.5 v "l" level input voltage v il ttl level input (note 2) C0.5 +0.8 v "h" level output voltage v oh i oh = C1, C8 ma 2.2 v "l" level output voltage v ol i ol = 1.8 ma 0.4 v "h" level input current i ih v ih = v dd 0.01 1 m a "l" level input current i il v il = v ss C1 C0.01 m a v il = v ss (with 100 k w pull-up) C120 C35 C5 m a i ozh v oh = v dd 0.01 1 m a three-state output leakage current i ozl v ol = v ss C1 C0.01 m a v ol = v ss (with 100 k w pull-up) C120 C35 C5 m a supply current (stand by) i dds output non-load (v ih = v dd , v il = v ss ) 0.1 10 m a supply current (operating) i ddo output non-load (v ih = v dd , v il = v ss ) f = 10 mhz 20ma (v dd = 2.7 v to 3.6 v, v ss = 0 v, tj = C40c to +85c) parameter symbol condition min. typ. max. unit "h" level input voltage v ih ttl level input (note 2) 2.2 v dd + 0.5 v "l" level input voltage v il ttl level input (note 2) C0.5 +0.8 v "h" level output voltage v oh i oh = C2, C16 ma 3.7 v "l" level output voltage v ol i ol = 2, 16 ma 0.4 v "h" level input current i ih v ih = v dd 0.01 10 m a "l" level input current i il v il = v ss C1 C0.01 m a v il = v ss (with 50 k w pull-up) C250 C100 C20 m a i ozh v oh = v dd 0.01 10 m a three-state output leakage current i ozl v ol = v ss C10 C0.01 m a v ol = v ss (with 50 k w pull-up) C250 C100 C20 m a supply current (stand by) i dds output non-load (v ih = v dd , v il = v ss ) 0.1 100 m a supply current (operating) i ddo output non-load (v ih = v dd , v il = v ss ) f = 10 mhz 40ma (v dd = 4.5 v to 5.5 v, v ss = 0 v, tj = C40c to +85c)
13/50 msm60804 ? semiconductor symbol min. max. unit parameter 20 0 30 30 20 100 100 35 40 30 25 25 20 12 20 55 55 55 55 55 85 15 10 10 5 55 50 45 t 1a t 1b t 1 t 5 t 3 t 6a t 6b t 18 t 2a t 2b t 19 t 20 t 4 t 5a t 5b t p1a t p1b t p2a t p2b t p3a t p3b t 14 t 15 t 9 t 10 t 11 t 13 t piola la <23:17> setup time to bale inactive la <23:17> hold time from bale inactive mc16 delay time from la <23:17> valid mc16 delay time from la <23:17> invalid sa [16:0] setup time to command active memr , memw pulse width iord , iowr pulse width mc16 delay time from sa [16:0] active ic16 delay time from sa [16:0] active ic16 delay time from command inactive nws delay time from command active nws delay time from command inactive delay time from command active to irdy inactive delay time from away , bwat active to irdy inactive delay time from away , bwat inactive to irdy active aa [25:0], ba [25:0] delay time from sa [16:0] valid aa [25:0], ba [25:0] delay time from sa [16:0] invalid delay time from command active to oe , we valid hold time from command inactive to oe , we valid delay time from sa [16:0] valid to ce , reg valid hold time from sa [16:0] invalid to ce , reg invalid aen inactive setup time to command active aen hold time from command inactive data valid setup time to iowr inactive data valid setup hold time from iowr inactive sd [7:0] data delay time from iord active sd [7:0] data hold time from iord inactive ior, iow delay time from command ns ac characteristics ac timing conditions
14/50 msm60804 ? semiconductor timing diagram 8/16-bit memory cycle ) * 9 : < = t 1b la [23:17] t 1a address valid address valid t 3 t 6a t 5 t 1 bale sa [16:0] sbhe memr , memw 9 : > ? t 18 t 4 t 19 t 20 t 5a t 5b t p1a t p1b address valid t p2a t p2b t p3b t p3a mc16 irdy nws awat bwat aa [25:0] ba [25:0] aoe , awe boe , bwe ace1 , ace2 , areg bce1 , bce2 , breg - . /
15/50 msm60804 ? semiconductor 8/16-bit i/o cycle & ' . / % & ! " ) * ! " bale address valid address valid t 1a t 14 t 15 t 6b aen la [23:17] sa [16:0] sbhe iord , iowr t 2a t 4 t 19 t 20 t 5a t p1a t p1b address varid t 10 t 10 t p3b t p3a ic16 irdy nws awat bwat aa [15:0] ba [15:0] aior , aiow bior , biow ace1 , ace2 , areg bce1 , bce2 , breg t 2b t 5b
16/50 msm60804 ? semiconductor register access ) * . / 5 6 1 2 bale address valid address valid (a16=0) t 1a t 14 t 15 t 6b t 11 t 13 t 9 t 10 aen la [23:17] la [16:0] sbhe iord , iowr sd [7:0] (in) write sd [7:0] (out)
17/50 msm60804 ? semiconductor interrupt request by a card status change status change irq# enable interrupt clear interrupt request from i/o card inturrupt csc event (in) irq# (out) ireq (in) irq# (out) irq# enable interrupt clear z z edge trigger mode interrupt request by a card status change interrupt request from i/o card csc event (in) irq# (out) ireq (in) irq# (out) irq# enable irq# enable status change interrupt interrupt clear interrupt clear z z level mode
18/50 msm60804 ? semiconductor functional description the msm60804 offers pc card interface which is functionally compatible to the intel se82365sl. the msm60804 supports the isa on its system interface side and function to control 2 slots of the pcmcia2.1 or jeida.2 on its card interface side. for details of pins and registers, see "pin description" and "register description". power control ? the msm60804 supplies 5 v or 3 v power to the pcic core and to the interface buffer on the system side. ? this power is supplied through the vccisa and vcccore pins. ? the vccisa voltage must be equal to the vcccore voltage. ? the interface buffer on the system side supports 5 v or 3 v cmos and 5 v or 3 v ttl interface levels. ? the levels are selected by the isapwr signal. ? power supply voltage to the interface buffer on the card side is selected to each slot from either 5 v or 3 v according to the rated voltage of the pc card inserted into each slot. ? power is supplied to the interface buffer on the card side through the vcca and vccb pins. ? voltages supplied to vcca and vccb and voltages supplied to slots are determined by controlling the external power supply circuit by vccen0 and vccen1. ? the vccev0 and vccen1 outputs are determined by the voltage control registers (+17h and +57h). ? the voltage of vpp power supplied to card slots are determined by controlling the external supply by the v10 and v11 pins. ? the v10 and v11 outputs are determined by the power control registers (+02h and +42h). memory access ? the memory address space of the pc card supports both attribute memory and common memory (maximum 64m bytes each). ? attribute memory or common memory is selected by the reg signal. ? the reg signal output is determined by the following two registers: interrupt and general-purpose register (+03h or +43h) card memory offset address # high byte register ? accessing to the memory space of the pc card is made through the memory address mapping window. ? the memory address mapping window allocates the following three addresses as shown below: system memory mapping start address system memory mapping offset address card memory offset address
19/50 msm60804 ? semiconductor system address space card address space window 0000000h stop address 110xxxh start address 100xxxh 0020xxxh 0010xxxh offset address 3f10xxxh 3ffffffh memory window mapping (example) ? the above addresses (to each window) are set by the following registers: system memory address # mapping start low byte register system memory address # mapping start high byte register system memory address # mapping stop low byte register system memory address # mapping stop high byte register card memory offset address # low byte register card memory offset address # high byte register ? up to 16mb can be allocated to a signal memory address mapping window. ? the window size is assigned by 4kb units. ? five windows can be allocated to each slot. ? each window is enabled by setting the following register: address window enable register (+06h or +46h) ? the msm60804 supports both 8-bit and 16-bit accessing modes on both systems interface and card interface sides. ? on the system interface side, the 8-bit and 16-bit accessing modes are switched by the sbhe signal. ? on the card interface side, the accessing method is determined by combinations of ce1 and ce2 signals. ? the values of ce1 and ce2 signals are set by a0 and the system memory address # mapping start high byte register.
20/50 msm60804 ? semiconductor ? a wait can be set for a memory access cycle of the pc card. ? a wait can be set for irdy by a wait signal from the card. ? a wait can be set for each system clock cycle by the following register: system memory address # mapping start high byte register ? the 0-wait state is reported to the nws pin by the following register: system memory address # mapping start high byte register i/o access ? the i/o address space of the pc card is 0 to ffffh. ? accessing to an i/o card is enabled by reg , oe , and we signals. ? accessing to the i/o address space of the pc card is made through the i/o address mapping window. ? the i/o address mapping window allocates the following two addresses: i/o address mapping start address i/o address mapping stop address ? the above address (for each window) is set by the following registers: i/o address # mapping start low byte register i/o address # mapping start high byte register i/o address # mapping stop low byte register i/o address # mapping stop high byte register ? an i/o address space of 0 to fffh can be allocated to each single i/o address mapping window. ? the window size is a multiple of 1 byte. ? two windows can be allocated to each slot. ? each window is enabled by setting the following register: address window enable register (+06h and +46h) ? the msm60804 supports both 8- bit and 16-bit accessing modes on both system interface and card interface sides. ? on the system interface side, the 8-bit and 16-bit accessing modes are switched by the sbhe signal. ? on the card interface side, the accessing method is determined by combinations of ce1 and ce2 signals. ? ce1 and ce2 signals are set by a0, iois16 and the i/o control register (+07 and 47h). ? a wait can be set for an i/o access cycle of the pc card. ? a wait can be set for irdy by a wait signal from the card. ? a wait can be set for each system clock cycle by the following register: i/o control register (+07 and +47h) ? the 0-wait state is transferred to the nws pin by the following register: i/o control register (+07 and +47h)
21/50 msm60804 ? semiconductor pcic register access ? the msm60804 provides a 40h register space for each slot. ? the register address of slot a is 3fh and the register address of slot b is 40h to 7fh. ? when two msm60804 chips are cascaded, register addresses are decoded according to the status of the sel0 signal. register addresses of slot c and slot d are respectively 80h to bfh and c0h to ffh. sel 0 base address index slot 0 0h 0h-3fh 0 (a) 0 0h 40h-7fh 1 (b) 1 80h 80h-bfh 2 (a) 1 80h c0h-ffh 3 (b) ? accessing to the register address space is indirect addressing through i/o addresses of 3e0h and 3e1h. ? the i/o address 3e0h specifies the register address to be accessed. ? the i/o address 3e1h accesses a register specified by 3e0h. selection of memory mode or i/o mode ? the memory pc card access mode and the i/o pc card access mode are switched by register setting. ? a pc card access mode is selected by the following register: interrupt & general control register (+03h and +43h) ? functions of a specific pin of the pcmcia are switched by mode switching. detection of card interface status ? the msm60804 detects the following seven pc card statuses and reflects them upon register values: ? the seven states are as follows: card detection ( cd1 or cd2 ) card power supply active (v10 or v11) voltage sense (vss0 or vss1) ready/busy (rdy) (for memory cards only) write protect (wp) (for memory cards only) battery voltage detect (bv1 or bv2) (for memory cards only) status change (bv1) (for i/o mode only) ? the detected state is reflected upon the following two registers: interface status register (+02h and +42h) voltage control register (+17h and +57h)
22/50 msm60804 ? semiconductor reset control ? the msm60804 is reset by the rstd signal from the system. ? it is possible to read only the configuration register when the pc card is removed by setting it on the register. ? resetting of the configuration register is enabled by the following register: card detection & general control register (+16h and +56h) for configuration registers, see the configuration register list. ? the pc card in each slot can be reset individually by register setting. ? set the following register to reset the pc card: interrupt & general control register (+03h and +43h) interrupt control ? the msm60804 supports interrupts by the ireq signals from pc cards and interrupts due to card status changed. ? these interrupts can be assigned to each slot. ? the interrupt by the ireq signal can be assigned to one of the irq pins. ? this assignment is set by the following register: interrupt & general control register (+03 and +43h) ? the interrupt due to card status changed can be assigned to one of the irq numbers or to ichk . ? this assignment is set by the following registers: interrupt & general control register (+03h and +43h) card status change interrupt configuration register (+05h and +45h) ? edge triggering or level triggering can be selected. ? this selection is set by the following register: general control register (+1eh ad +5eh) power-down control ? the msm60804 supports the power-down mode. this mode can be set for each slot. ? the power-down mode can be set by the following register: voltage control register (+17h and +57h) cascade connection ? by internal decoding of register address, it is possible to connect two msm60804 chips in a cascade manner and to support four slots simultaneously. ? when the base address is set by the spkr or sel0 input, the register address of the second msm60804 is assigned to 80h to ffh.
23/50 msm60804 ? semiconductor registers msm60804 register table slot a offset slot b offset +00h +40h register name identification and revision +01h +41h interface status +02h +42h power control +03h +43h interrupt and general control +04h +44h card status change +05h +45h card status change interrupt configuration +06h +46h address window enable +07h +47h i/o control +08h +48h i/o address 0 start low byte +09h +49h i/o address 0 start high byte +0ah +4ah i/o address 0 stop low byte +0bh +4bh i/o address 0 stop high byte +0ch +4ch i/o address 1 start low byte +0dh +4dh i/o address 1 start high byte +0eh +4eh i/o address 1 stop low byte +0fh +4fh i/o address 1 stop high byte +10h +50h +11h +51h system memory address 0 mapping start low byte +12h +52h system memory address 0 mapping start high byte +13h +53h system memory address 0 mapping stop low byte +14h +54h system memory address 0 mapping stop high byte +15h +55h card memory offset address 0 low byte +16h +56h card memory offset address 0 high byte +17h +57h card detect and general control +18h +58h voltage control register +19h +59h system memory address 1 mapping start low byte +1ah +5ah system memory address 1 mapping start high byte +1bh +5bh system memory address 1 mapping stop low byte +1ch +5ch system memory address 1 mapping stop high byte +1dh +5dh card memory offset address 1 low byte +1eh +5eh card memory offset address 1 high byte +1fh +5fh global control +20h +60h reserved +20h +61h system memory address 2 mapping start low byte +22h +62h system memory address 2 mapping start high byte +23h +63h system memory address 2 mapping stop low byte +24h +64h system memory address 2 mapping stop low byte +25h +65h card memory offset address 2 low byte card memory offset address 2 high byte
24/50 msm60804 ? semiconductor msm60804 register table (continued) slot a offset slot b offset +26h +66h register name reserved +27h +67h reserved +28h +68h system memory address 3 mapping start low byte +29h +69h system memory address 3 mapping start high byte +2ah +6ah system memory address 3 mapping stop low byte +2bh +6bh system memory address 3 mapping stop high byte +2ch +6ch card memory offset address 3 low byte +2dh +6dh card memory offset address 3 high byte +2eh +6eh reserved +2fh +6fh reserved +30h +70h system memory address 4 mapping start low byte +31h +71h system memory address 4 mapping start high byte +32h +72h system memory address 4 mapping stop low byte +33h +73h system memory address 4 mapping stop high byte +34h +74h card memory offset address 4 low byte +35h +75h card memory offset address 4 high byte +36h +76h +37h +77h oki revision +38h +78h reserved +39h +79h reserved +3ah +7ah reserved +3bh +7bh reserved +3ch +7ch reserved +3dh +7dh reserved +3eh +7eh reserved +3fh +7fh reserved reserved
25/50 msm60804 ? semiconductor pcic revision register the identification and revision register, as shown below is for read purposes only. 83h can be read from the identification and revision register, similar to the 82365sl (step b). d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base +00h) slot b : index value (base +40h) pcic revision bit 0 pcic revision bit 1 pcic revision bit 2 pcic revision bit 3 0 0 pcic interface id bit 0 pcic interface id bit 1 identification and revision register (read only) oki revision register the oki revision register, as shown below, is for read purposes only. d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base +36h) slot b : index value (base +76h) support slot bit 0 support slot bit 1 revision bit 0 revision bit 1 oki id bit 0 oki id bit 1 oki id bit 2 oki id bit 3 oki revision register (read only) the oki revision register shows the id number of an oki chip (b2h), as shown below. oki revision register bits values id 1011 revision 00 support slot 10
26/50 msm60804 ? semiconductor interface status register the interface status register is shown below. the bits are defined below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base + 01h) slot b : index value (base + 41h) battery voltage detect 1 battery voltage detect 1 card detect 1 card detect 2 memory write protect ready/ busy pc card power active reserved interface status register (read only) d bits description bit 6 pc card power active. when set to "1", this bit indicates that v pp1 and v pp2 are active. when set to "0", this bit indicates that v pp1 and v pp2 are inactive. bit 5 ready/ busy . when set to "1", this bit indicates that rdy/ bsy is active (rdy/ bsy = "1"). when set to "0", this bit indicates that rdy/ bsy is inactive (rdy/ bsy = "0"). bit 4 bit 3 bit 2 bit 1 bit 0 memory write protect. when set to "1", this bit indicates that wp is active (wp = "1"). when set to "0", this bit indicates that wp is inactive (wp = "0"). card detect 2. when set to "1", this bit indicates that cd2 is active ( cd2 = "0"). when set to "0", this bit indicates that cd2 is inactive ( cd2 = "1"). card detect 1. when set to "1", this bit indicates that cd1 is active ( cd1 = "0"). when set to "0", this bit indicates that cd1 is inactive ( cd1 = "1"). battery voltage detect 2. when set to "1", this bit indicates that bvd2 is active (bvd2 = "1"). when set to "0", this bit indicates that bvd2 is inactive (bvd2 = "0"). in the case of id card mode, this bit indicates the skpr status. battery voltage detect 1. when set to "1", this bit indicates that bvd1 is active (bvd1 = "1"). when set to "0", this bit indicates that bvd1 is inactive (bvd1 = "0"). in the case of id card mode, this bit indicates the stschg status. interface status register description
27/50 msm60804 ? semiconductor the output statuses of cd1 and cd2 signals are shown below output status of cd1 and cd2 signals status cd2 cd1 the card is inserted 0 0 the card has been taken out 1 0 the card has been taken out 0 1 the card has been completely removed (used for resetting) 1 1 bv1 and bv2 signals show the memory card battery status. signals and the corresponding battery status are shown below. corresponding status status bv2 bv1 battery dead 0 0 battery dead 1 0 battery warning 0 1 battery good 1 1
28/50 msm60804 ? semiconductor card power control the card power control function block controls v10 and v11. power control register the power control register is shown below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base+02h) slot b : index value (base+42h) v10 control bit 0 v11 control bit 1 reserved reserved power enable auto power switch enable reserved output enable power control register (read/write)
29/50 msm60804 ? semiconductor output enable and power active states power control register card detection tri-state output bit 6 of interface status register (+01h)-bit 6 bit 5 bit 7 bit 4 cd1 cd2 0 off 0 0 1 0 0 off 1 1 100 on 1 0 1 1 off 1 0 11 off 1 1 1 1 off 0 1 11 off 0 *a [25:0], ce1 , ce2 , iord , iowr , oe , reg , rst, we below are explained the relationships between the states of v10 and v11 and power control bits (bit 0 and bit 1) and bit 6 of the interface status register (+01h). v10, v11 control bit 1 bit 0 v 10 v 11 +01h (bit 6) 0 0 1 00 0 0 0 01 1 0 0 10 0 1 0 11 0 0 0
30/50 msm60804 ? semiconductor interrupt and general control register the interrupt and general control registers is shown below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base+03h) slot b : index value (base+43h) irq bit 0 irq bit 1 irq bit 2 irq bit 3 iochk enable pc card type pc card reset reserved interrupt and general control register (read/write) reset signal pc card register description bits description bit 6 bit 5 bit 4 pc card reset when this bit is set to "0", a pc card reset signal is output. pc card type when this bit is set to "1", the i/o card mode is enabled. when this bit is set to "0", the memory card mode is enabled. ichk enable when this bit is set to "1", the status change interrupt is output to the ichk pin. see "card status change interrupt configuration registers". irq bits (bit 0 to bit 3) determine the output pin to which an interrupt due to ireq (rdy/bsy pin is the i/o mode) will be output. see the table below.
31/50 msm60804 ? semiconductor ireq level selected by interrupt general control register irq bit 3 irq bit 2 irq bit 1 irq bit 0 ireq level 0000 not selected 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 not selected not selected irq3 irq4 irq5 not selected irq7 not selected irq9 irq10 irq11 irq12 not selected irq14 irq15
32/50 msm60804 ? semiconductor card status change register the card status change register indicates the cause of an interrupt, as shown below. the bits are defined below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base+04h) slot b : index value (base+44h) battery dead / stschg battery warning ready change card detect change reserved reserved reserved reserved card status change register (read/write) card status change register description bits description bit 3 bit 2 bit 1 bit 0 card detect change. when set to "1", this bit indicates cd1 and cd2 signal status change (l ? h). ready change. when set to "1", this bit indicates a rdy/ bsy signal change(l ? h). battery warning. when set to "1", this bit indicates a battery warning status change (good ? warning, dead ? warning). battery dead. when set to "1", this bit indicates a battery dead status change (good ? dead, warning ? dead). note that a stschg signal status change has taken place in i/o card mode. when the card status change explicit write back notification bit of the general control register (+1eh, +5eh) is "0", the contents of the register are cleared and the interrupt is canceled, by reading this register.
33/50 msm60804 ? semiconductor card status change interrupt configuration register the card status change interrupt configuration register is shown below. the bits are defined below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base +05h) slot b : index value (base +45h) battery dead enable / stschg enable battery warning enable ready enable card detect enable irq bit 0 irq bit 1 irq bit 2 irq bit 3 card status interrupt configuration register (read/write) card status interrupt configuration register description bits description bit 3 bit 2 bit 1 bit 0 card detect enable. when set to "1", this bit enables an interrupt by cd1 and cd2 status change. when set to "0", this bit disables an interrupt by cd1 and cd2 status change common to both memory and i/o modes. battery warning enable. in the memory mode, when set to "1", this bit enables an interrupt to battery warning state(good ? warning, dead ? warning). when set to "0", this bit disables an interrupt to battery warning state (good ? warning, dead ? warning). ready enable. in the memory mode, when set to "1", this bit enables an interrupt to rdy/ bsy (l ? h). when set to "0", this bit disables an interrupt to rdy/ bsy (l ? h). battery dead enable. in the memory mode, when set to "1", this bit enables an interrupt to battery dead state (good ? dead, warning ? dead) and also enables an interrupt to the stschg signal status change in i/o card mode. when set to "0", this bit disables battery state interrupt stschg change interrupt.
34/50 msm60804 ? semiconductor irq bits 0 to 3 set the irq level selection as follows. when ichk enable bit is "1", ichk interrupt signal is selected independently of irq bits setting. ichk enable bit irq bit 3 irq bit 2 irq bit 1 irq level irq bit 0 0000 not selected 0 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 1 not selected not selected irq3 irq4 irq5 not selected irq7 not selected irq9 irq10 irq11 irq12 not selected irq14 irq15 ichk
35/50 msm60804 ? semiconductor address window enable register the address window enable register is shown below. the bits are defined below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base+06h) slot b : index value (base+46h) memory window 0 enable memory window 1 enable memory window 2 enable memory window 3 enable memory window 4 enable mc16 decode a [23:12] i/o window 0 enable i/o window 1 enable address window enable register (read/write) address window enable register description bits description bit 6 bit 7 bit 4 bit 5 bit 2 bit 3 bit 0 bit 1 i/o window 1 enable. when set to "1", this bit enables the i/o window 1. i/o window 0 enable. when set to "1", this bit enables the i/o window 0. mc16 decode a [23:12] when this bit is set to "1", sa [23:12] is decoded into an mc16 signal. when this bit is set to "0", la [23:17] is decoded into an mc16 signal. memory window 4 enable when this bit is set to "1", memory window 4 is enabled. memory window 3 enable when this bit is set to "1", memory window 3 is enabled. memory window 2 enable when this bit is set to "1", memory window 2 is enabled. memory window 1 enable when this bit is set to "1", memory window 1 is enabled. memory window 0 enable when this bit is set to "1", memory window 0 is enabled.
36/50 msm60804 ? semiconductor i/o control register the i/o control register is shown below. the bits are defined below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base+07h) slot b : index value (base+47h) i/o window 0 data size i/o window 0 ic16 source i/o window 0 zero_ws i/o window 0 wait state i/o window 1 data size i/o window 1 ic16 source i/o window 1 zero_ws i/o window 1 wait state i/o control register (read/write) i/o control register description bits description bit 7/bit 3 bit 6/bit 2 bit 5/bit 1 bit 4/bit 0 i/o window 1 wait state/ i/o window 0 wait state. when these bits are set to "1" and a 16-bit i/o access is carried out, an irdy signal is made low for 1 sclk cycle as a 1 wait request. it is invalid in 8-bit i/o access. i/o window 1 zero wait state i/o window 0 zero wait state. when these bits are set to "1" and an 8-bit i/o access is carried out, nws signal is effective. i/o window ic16 source i/o window 0 ic16 source. when these bits are set to "1", an ic16 signal is generated from an iois16 signal:when these bits are set to "0", an ic16 signal is generated from bit 4/bit 0. i/o window 1 data size i/o window 0 data size. when these bits are set to "1", a 16-bit access is enabled: when these bits are set to "0", an 8-bit access is enabled. ce1, ce2 and output control bit 1, 5 bit 0, 4 iois16 sbhe a0 is16 ce2 ce1 01 00 0 0 0 01 01 0 0 1 01 1 0 1 0 00 1 1 0 1 000 0 0 0 1 001 0 0 1 1 01 0 1 0 1 1 1 1 0
37/50 msm60804 ? semiconductor i/o address # start low byte register the i/o address # start low byte register is shown below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : window 0 index value (base + 08h) slot a : window 1 index value (base + 0ch) slot b : window 0 index value (base + 48h) slot b : window 1 index value (base + 4ch) address 0 address 1 address 2 address 3 address 4 address 5 address 6 address 7 i/o address # start low byte register (read/write) i/o address # start high byte register the i/o address # start high byte register is shown below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : window 0 index value (base + 09h) slot a : window 1 index value (base + 0dh) slot b : window 0 index value (base + 49h) slot b : window 1 index value (base + 4dh) address 8 address 9 address 10 address 11 address 12 address 13 address 14 address 15 i/o address # start high byte register (read/write)
38/50 msm60804 ? semiconductor i/o address # stop low byte register the i/o address # stop low byte register is shown below. i/o address # stop low byte register (read/write) i/o address # start high byte register the i/o address # start high byte register is shown below. i/o address # stop high byte register (read/write) d7 d6 d5 d4 d3 d2 d1 d0 slot a : window 0 index value (base +0ah) slot a : window 1 index value (base +0eh) slot b : window 0 index value (base +4ah) slot b : window 1 index value (base +4eh) address 0 address 1 address 2 address 3 address 4 address 5 address 6 address 7 d7 d6 d5 d4 d3 d2 d1 d0 address 8 address 9 address 10 address 11 address 12 address 13 address 14 address 15 slot a : window 0 index value (base +0bh) slot a : window 1 index value (base +0fh) slot b : window 0 index value (base +4bh) slot b : window 1 index value ( base +4fh )
39/50 msm60804 ? semiconductor system memory address # mapping start low byte register the system memory address # mapping start low byte register is shown below. d7 d6 d5 d4 d3 d2 d1 d0 slot a: window 0 index value (base + 10h) slot a: window 1 index value (base + 18h) slot a: window 2 index value (base + 20h) slot a: window 3 index value (base + 28h) slot a: window 4 index value (base + 30h) slot b: window 0 index value (base + 50h) slot b: window 1 index value (base + 58h) slot b: window 2 index value (base + 60h) slot b: window 3 index value (base + 68h) slot b: window 4 index value (base + 70h) address 12 address 13 address 14 address 15 address 16 address 17 address 18 address 19 system memory address # mapping start low byte register (read/write) system memory address # mapping start high byte register the system memory address # mapping start high byte register is shown below. d7 d6 d5 d4 d3 d2 d1 d0 slot a: window 0 index value (base + 11h) slot a: window 1 index value (base + 19h) slot a: window 2 index value (base + 21h) slot a: window 3 index value (base + 29h) slot a: window 4 index value (base + 31h) slot b: window 0 index value (base + 51h) slot b: window 1 index value (base + 59h) slot b: window 2 index value (base + 61h) slot b: window 3 index value (base + 69h) slot b: window 4 index value ( base + 71h ) address 20 address 21 address 22 address 23 reserved reserved zero wait state data size system memory address # mapping start high byte register (read/write)
40/50 msm60804 ? semiconductor bits description bit 7 bit 6 data size when this bit is set to "0", 8-bit memory accessing is enabled. when this bit is set to "1", 16-bit memory accessing by mc16 is enabled. zero wait enabled. when this bit is set to "0", nws signal is not generated. when this bit is set to "1" and the irdy pin is high, the nws signal is generated. note that the nws signal does not become active, when 8-bit accessing, a0 = "0" and sbhe = "0". system memory address # mapping start high byte register description control ce1 and ce2 bit 7 1 1 1 0 sbhe 0 0 1 a0 0 1 ce1 0 1 0 0 ce2 0 0 1 1 mc16 0 0 0 1
41/50 msm60804 ? semiconductor the values set in the next two registers are the stop address of the memory windows. system memory address # mapping stop low byte register the system memory address # mapping stop low byte register is shown below. d7 d6 d5 d4 d3 d2 d1 d0 slot a: window 0 index value (base + 12h) slot a: window 1 index value (base + 1ah) slot a: window 2 index value (base + 22h) slot a: window 3 index value (base + 2ah) slot a: window 4 index value (base + 32h) slot b: window 0 index value (base + 52h) slot b: window 1 index value (base + 5ah) slot b: window 2 index value (base + 62h) slot b: window 3 index value (base + 6ah) slot b: window 4 index value ( base + 72h ) address 12 address 13 address 14 address 15 address 16 address 17 address 18 address 19 system memory address # mapping stop low byte register (read/write) system memory address # mapping stop high byte register the system memory address # mapping stop high byte register is shown below. d7 d6 d5 d4 d3 d2 d1 d0 slot a: window 0 index value (base + 13h) slot a: window 1 index value (base + 1bh) slot a: window 2 index value (base + 23h) slot a: window 3 index value (base + 2bh) slot a: window 4 index value (base + 33h) slot b: window 0 index value (base + 53h) slot b: window 1 index value (base + 5bh) slot b: window 2 index value (base + 63h) slot b: window 3 index value (base + 6bh) slot b: window 4 index value (base + 73h) address 20 address 21 address 22 address 23 reserved reserved wait state bit 0 wait state bit 1 system memory address # mapping stop high byte register (read/write)
42/50 msm60804 ? semiconductor system memory address # mapping stop high byte register description bits description bit 7/bit 6 wait status bits 0 and 1 these bits specify the duration (in sclk cycles) of a wait (low) given to irdy. this function is valid only in the 16-bit access. irdy output function start high byte register data size bit 7 bit 7 bit 6 irdy 0 high 1 0 0 high 1 0 1 1sclk cycle low 1 1 0 2sclk cycle low 1 1 1 3sclk cycle low
43/50 msm60804 ? semiconductor card memory offset address # low byte register the card memory offset address # low byte register is shown below. d7 d6 d5 d4 d3 d2 d1 d0 slot a: window 0 index value (base + 14h) slot a: window 1 index value (base + 1ch) slot a: window 2 index value (base + 24h) slot a: window 3 index value (base + 2ch) slot a: window 4 index value (base + 34h) slot b: window 0 index value (base + 54h) slot b: window 1 index value (base + 5ch) slot b: window 2 index value (base + 64h) slot b: window 3 index value (base + 6ch) slot b: window 4 index value (base + 74h) address 12 address 13 address 14 address 15 address 16 address 17 address 18 address 19 card memory offset address # low byte register (read/write) card memory offset address # high byte register the card memory offset address # high byte register is shown below. d7 d6 d5 d4 d3 d2 d1 d0 slot a: window 0 index value (base + 15h) slot a: window 1 index value (base + 1dh) slot a: window 2 index value (base + 25h) slot a: window 3 index value (base + 2dh) slot a: window 4 index value (base + 35h) slot b: window 0 index value (base + 55h) slot b: window 1 index value (base + 5dh) slot b: window 2 index value (base + 65h) slot b: window 3 index value (base + 6dh) slot b: window 4 index value (base + 75h) address 20 address 21 address 22 address 23 address 24 address 25 reg active write protect card memory offset address # high byte register (read/write)
44/50 msm60804 ? semiconductor card memory offset address # high byte register description bits description bit 7 bit 6 write protect : when this bit is set to "1", wp signal is made to "h" and write protect is enabled forcibly. reg active : when this bit is set to "1", attribute memory space access is enabled by the active reg signal output. card detect and general control register the card detect and general control register is shown below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base + 16h) slot b : index value (base + 56h) 16 bit memory delay inhibit configuration reset enable reserved reserved status change mask software card detect interrupt reserved reserved card detect and general control register (read/write) card detect and general control register description bits description bit 5 bit 4 status change mask when this bit is set to "1", all interrupts due to status transitions are disabled. this masking is done regardless of the status of each enable bit of the card status change interrupt configuration registers (+05h and +45h). software card detect interrupt : when this bit is set to 1 while the card detect change enable bit 4 of the card status change interrupt configuration register (+05h) is set to "1", a card detect change interrupt is generated the same as a hardware card detect interrupt. note : the software card detection interrupt bit is always reset to "0" when the card status change register is read.
45/50 msm60804 ? semiconductor configuration register setting configuration register reset bit 1 cd1 no 0 yes 1 0 cd2 0 configuration registers are shown on the next page.
46/50 msm60804 ? semiconductor the configuration registers are shown below. configuration registers slot a offset slot b offset +03h +43h register name +06h +46h +07h +47h +08h +48h +09h +49h +0ah +4ah +0bh +4bh +0ch +4ch +0dh +4dh +0eh +4eh +0fh +4fh +10h +50h +11h +51h +12h +52h +13h +53h +14h +54h +15h +55h +18h +58h +19h +59h +1ah +5ah +1bh +5bh +1ch +5ch +1dh +5dh +20h +60h +21h +61h +22h +62h +23h +63h +24h +64h +25h +65h +28h +68h +29h +69h +2ah +6ah +2bh +6bh +2ch +6ch +2dh +6dh +30h +70h +31h +71h +32h +72h +33h +73h +34h +74h +35h +75h interrupt and general control (except ichk enable bit) address window enable (except mc16 decode a[23:12] bit) i/o control i/o address 0 start low byte i/o address 0 start high byte i/o address 0 stop low byte i/o address 0 stop high byte system memory address 0 mapping start low byte system memory address 0 mapping start high byte system memory address 0 mapping stop low byte system memory address 0 mapping stop high byte card memory offset address 0 low byte card memory offset address 0 high byte i/o address 1 start low byte i/o address 1 start high byte i/o address 1 stop low byte i/o address 1 stop high byte system memory address 1 mapping start low byte system memory address 1 mapping start high byte system memory address 1 mapping stop low byte system memory address 1 mapping stop high byte card memory offset address 1 low byte card memory offset address 1 high byte system memory address 2 mapping start low byte system memory address 2 mapping start high byte system memory address 2 mapping stop low byte system memory address 2 mapping stop high byte card memory offset address 2 low byte card memory offset address 2 high byte system memory address 3 mapping start low byte system memory address 3 mapping start high byte system memory address 3 mapping stop low byte system memory address 3 mapping stop high byte card memory offset address 3 low byte card memory offset address 3 high byte system memory address 4 mapping start low byte system memory address 4 mapping start high byte system memory address 4 mapping stop low byte system memory address 4 mapping stop high byte card memory offset address 4 low byte card memory offset address 4 high byte
47/50 msm60804 ? semiconductor bit description bit 0 16-bit memory delay inhibit. when this bit is set to "0" if 16-bit access (bit7 of system memory address # mapping start high byte register is "1"), we and oe signals are output by one-stage synchronization of imemw and imemr , at the falling edge of isysclk. when this bit is set to "1", we and oe signals are always output asynchronously with isysclk. the timing diagram of sclk synchronization of we , oe is shown below. timing diagram of iwe , owe to sclk the sclk synchronization of we , oe is shown below. sclk synchronization of we , oe when bit 7 = "1" and bit 0 = "0" of sma # start hbr sclk when bit 0 = "1" memw memr oe we oe sclk sychronization of we , oe bit 7 of sma#m start hbr bit 0 no 0 yes 10 no 11
48/50 msm60804 ? semiconductor voltage control register the voltage control register is shown below. the bits are defined below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base + 17h) slot b : index value (base + 57h) card v cc control bit 0 card v cc control bit 1 voltage control voltage sense bit 0 voltage sense bit 1 reserved reserved power down select bit description bit 7 bit 4 bit 3 bit 2 bit 1 d bits bit 0 power down select : when set to "1", power down mode is set voltage sense bit 1 : this bit corresponds to state of v ss1 (voltage sense) pin voltage sense bit 0 : this bit corresponds to state of v ss0 (voltage sense) pin voltage_control. when set to "1", pcmcia input buffers will trigger to 5 v ttl levels: when set to "0", pcmcia input buffers will trigger to 3 v ttl or 3 v/5 v cmos input levels. card v cc control bit 1 card v cc control bit 0 to enter power down mode the following should be done: 1. bit 0 of global general control register (1e or 5e) is set to "1". 2. bit 7 of voltage control register 17 is set to "1". to leave the power down mode and enter a normal mode of operation the following should be done: 1. bit 7 of voltage control register (+17h, +57h) is set to "0". 2. bit 0 of global general control register (+1eh, +5eh) is set to "0". the power down mode affects only internal logic excluding registers +17h and +57h. v cc control bits are encoded as follows: bit 1 bit 0 vccen1 vccen0 description 0000 not connected 0100 reserved 1010 5.0 v 1101 3.3 v voltage control register (read/write) voltage control register description
49/50 msm60804 ? semiconductor global control register the global control register is shown below. the bits are defined below. d7 d6 d5 d4 d3 d2 d1 d0 slot a : index value (base + 1eh) slot b : index value (base + 5eh) power-down enable level mode interrupt enable explicit write interrupt enable irq14 pulse mode enable reserved reserved reserved reserved global control register (read/write) global control register description bits description bit 3 bit 1 bit 2 bit 0 irq14 pulse mode enable. when this bit is "1" and bit 1 is "0", an interrupt assigned to irq12 is set to level mode. note that when bit 1 is set to "1" for level mode this bit is ineffective. level mode interrupt enable. this bit selects a mode for an interrupt signal, which is output to the irq#. when set to "1", level mode interrupt is selected. when set to "0", edge-triggered mode interrupt is selected. while this bit is set to "1", the content of the card status change registers (+04h and +44h) will not be cleared after they are read. to clear the content of the register and reset the inturrupt, write "1" to the corresponding bit of the card status change register. if a status change interrupt is disabled by the card status change interrupt configuration registers (+05h and 45h) or the card detection control registers (+16h and +56h), even when a status change interrupt occurs while this bit is set to "1", the card status change register is cleared and the interrupt is reset. power-down enable when this bit is set to "1", the power down mode is enabled. when this bit is set to "0", the power down mode is disabled.
50/50 msm60804 ? semiconductor (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin cu alloy solder plating 5 m m or more 5.65 typ. qfp208-p-2828-0.50-bk4 mirror finish

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